| Design Name | sw2_pld_main |
| Fitting Status | Successful |
| Software Version | H.42 |
| Device Used | XCR3256XL-12-PQ208 |
| Date | 6-13-2006, 3:43PM |
| Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
|---|---|---|---|---|
| 219/256 (86%) | 541/768 (71%) | 127/256 (50%) | 116/160 (73%) | 519/640 (82%) |
| LCT0 | LCT1 | LCT2 | LCT3 | LCT4 | LCT5 | LCT6 | LCT7 | |
|---|---|---|---|---|---|---|---|---|
| FB1 | oe | clk | clk | |||||
| FB2 | oe | clk | ||||||
| FB3 | ||||||||
| FB4 | ||||||||
| FB5 | uct1 | |||||||
| FB6 | uct2 | |||||||
| FB7 | clk | |||||||
| FB8 | uct4 | |||||||
| FB9 | clk | |||||||
| FB10 | ||||||||
| FB11 | ||||||||
| FB12 | ||||||||
| FB13 | ||||||||
| FB14 | clk | |||||||
| FB15 | clk | |||||||
| FB16 | clk | clk |
| ce = clock enable | clk = clock | oe = output enable | sr = set/reset |
| uct1 = universal control term clock | uct2 = universal control term output enable | uct3 = universal control term preset | uct4 = universal control term reset |
|
|
| Signal mapped onto global clock net (GCK0) | CLK |
| Universal Control Terms (Used/Total) | 3/4 |
| Function Block Local Control Terms (Used/Total) | 14/128 |
| Foldback NANDs (Used/Total) | 0/128 |